Project Description:
The project involves designing and implementing a polynomial evaluation accelerator (PEA) that processes instructions from a control FIFO and data from a data FIFO to perform operations such as storing polynomials (STP), evaluating a single polynomial (EVP), evaluating multiple inputs (EVB), and resetting stored data (RST). The accelerator maintains up to eight polynomials (each with degree up to 10) and outputs both results and corresponding status codes indicating correct execution or specific errors (e.g., invalid degree or using an unset polynomial). The system must properly handle FIFO interactions, including stalling when inputs are unavailable or outputs are full, and must be implemented both in software (LIDE-C) and hardware (Verilog), with emphasis on correctness, performance, and design trade-offs.
