Project Description:
The Polynomial Evaluation Accelerator (PEA) is a streaming accelerator that evaluates polynomials of up to degree 10 over eight cached coefficient vectors using four instructions: STP, EVP, EVB, and RST. The software component implements the PEA as a LIDE-C actor following Core Functional Dataflow (CFDF) semantics, validated with unit tests and multi-instruction stream tests. The hardware component implements the PEA in synthesizable Verilog using the LIDE-V framework, with three Pareto-optimal designs synthesized using Vivado to explore the tradeoff between resource usage and clock frequency. All designs accept 16-bit signed inputs and produce 32-bit signed results, with instruction words encoded as 16-bit words containing a 2-bit opcode, 3-bit CV address, and 5-bit operand field.
